R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 551

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1. Check to make sure the DBSC2 is not being accessed. The time required for transition to self-
2. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 0 (access disabled).
3. Set the ARFEN bit in the SDRAM refresh control register 0 (DBRFCNT0) to 0 (automatic
4. Use the CMD bits in the SDRAM command control register (DBCMDCNT) to issue the
5. Use the CMD bits in DBCMDCNT to issue the REF (auto-refresh) command.
6. Set the SRFEN bit in DBRFCNT0 to 1 to make a transition to self-refresh mode.
7. Read DBRFCNT0, and make sure the SRFEN bit is set to 1.
8. Using the CPG setting, stop the clock to the DBSC2, or change the frequency.
Use the following procedure to cancel self-refresh mode.
1. Re-start the clock supply, and wait until the clock is being stably supplied to the DBSC2.
2. Writing to the DDRPAD frequency setting register (DBFREQ) enters the DLL settings.
3. Set the SRFEN bit in DBRFCNT0 to 0, to cancel self-refresh mode.
4. Use the software to wait until access to the DDR2-SDRAM is enabled. The value for this time
5. Use the CMD bits in DBCMDCNT to issue the REF (auto-refresh) command.
6. Set the ACEN bit in DBEN to 1 (access enabled).
7. Set the ARFEN bit in DBRFCNT0 to 1 (automatic issue of auto-refresh enabled). Normal
refresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or
some other causes.
issue of auto-refresh disabled).
PALL (precharge all banks) command.
A. Set DLLRST = 0.
B. Set the DDRPAD frequency in the FREQ bit.
C. After DLLRST = 1 has been set, use the software to wait the time necessary for the DLL to
period must be at least as long as the time until the non-read command is issued following
cancellation of the self-refresh status (tXSNR time) that is specified in the datasheet for the
SDRAM being used.
access is enabled after that point.
stabilize with the DDRPAD, which is at least 100 μs.
Rev.1.00 Jan. 10, 2008 Page 519 of 1658
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100