R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 410
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 410 of 1694
- Download datasheet (9Mb)
11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 378 of 1658
REJ09B0261-0100
Bit
27
26 to 24 ADH
23
22 to 20 RDS
Bit Name
⎯
⎯
Initial
Value
0
111
0
111
R/W
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Hold Cycle
These bits specify the number of cycles to be inserted
as the address hold time with respect to CSn negation.
(Only valid when the SRAM interface, byte control
SRAM interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
RD Setup Cycle (CSn Assertion–RD Assertion Delay
Cycle)
These bits specify the number of cycles to be inserted
as the time from CSn assertion to RD assertion. (Only
valid only when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted (1 cycle delayed)
001: 1 cycle inserted (2 cycles delayed)
010: 2 cycles inserted (3 cycles delayed)
011: 3 cycles inserted (4 cycles delayed)
100: 4 cycles inserted (5 cycles delayed)
101: 5 cycles inserted (6 cycles delayed)
110: 6 cycles inserted (7 cycles delayed)
111: 7 cycles inserted (8 cycles delayed)
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