R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 229

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.7.6
In TLB extended mode, the names of the data arrays have been changed from UTLB data array to
UTLB data array 1, UTLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB
extended mode, the PR and SZ bits of UTLB data array 1 are reserved and 0 should be specified
as the write value for these bits. In addition, when a write to UTLB data array 1 is performed, a
write to UTLB data array 2 of the same entry should always be performed after that.
In TLB compatible mode (MMUCR.ME = 0), UTLB data array 2 cannot be accessed. Operation if
they are accessed is not guaranteed.
(1)
In TLB extended mode, bits 7 to 4 in the data field, which correspond to the PR and SZ bits in
compatible mode, are reserved. Specify 0 as the write value for these bits.
UTLB Data Array 1
Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode)
Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode)
UTLB Data Array (TLB Extended Mode)
Address field
Address field
Data field
Data field
Legend:
PPN:
V:
E:
D:
*:
31
31
1 1 1 1 0 1 1 1 0 0 0 0
Physical page number
Validity bit
Entry
Dirty bit
Don't care
31
31
1 1 1 1 0 1 1 1 0 0 0 0
PPN:
SZ:
D:
29 28
V:
E:
* :
29 28
Physical page number
Validity bit
Entry
Page size bits
Dirty bit
Don't care
20 19
PPN
20
C:
SH:
WT:
PPN
*
19
:
*
* *
Cacheability bit
Share status bit
Write-through bit
Reserved bits
(write value should be 0,
and read value is undefined)
*
WT:
PR:
SH:
* * * *
C:
* * *
:
Protection key data
Cacheability bit
Share status bit
Write-through bit
Reserved bits (write value should be 0
and read value is undefined )
14 13
14 13
Rev.1.00 Jan. 10, 2008 Page 197 of 1658
E
10 9 8 7
E
10 9 8 7
7. Memory Management Unit (MMU)
8 7
V
V
8 7
* * * * * *
* * * * * *
6 5
SZ1
PR
4 3
4 3
C D
C
2 1
2 1 0
2 1
2 1
D
SH
REJ09B0261-0100
0
SH
0 0
WT
0
0
0
0
WT