R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 723

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
2
1
Bit Name
AE
NMIF
Initial
Value
0
0
R/W
R/(W)* Address Error Flag
R/(W)* NMI Flag
Descriptions
Indicates that an address error occurred during DMA
transfer.
This bit is set under following conditions.
•
•
•
When the AE bit in DMAOR0 is set, DMA transfers for
channels 0 to 5 are disabled even if the DE bit in CHCR
of the channels (channels 0 to 5) corresponding to
DMAOR0 and the DME bit in DMAOR0 are set to 1.
When the AE bit in DMAOR1 is set, DMA transfers for
channels 6 to 11 are disabled even if the DE bit in
CHCR of the channels (channels 6 to 11)
corresponding to DMAOR1 and the DME bit in
DMAOR1 are set to 1.
0: No DMAC address error
1: DMAC address error occurs
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR
and the DME bit in DMAOR are set to 1.
When the NMI is input, the DMA transfer is stopped.
Set registers of all channels again after returning from
the exception handling routine of a NMI and then start a
transfer. When the DMAC does not operate, the NMIF
bit is set to 1 even if the NMI interrupt is input.
0: No NMI interrupt
1: NMI interrupt occurs
[Clearing condition]: Write 0 to the AE bit after the bit
is read as 1
[Clearing condition]: Write 0 to NMIF after NMIF is
read as 1
The value set in SAR or DAR does not match to the
transfer size boundary.
The transfer source or transfer destination is
undefined space on the address map.
The transfer source or transfer destination is in
module stop mode
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 691 of 1658
REJ09B0261-0100