R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 748

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 716 of 1658
REJ09B0261-0100
(a) CH0:
(b) CH0:
(c) CH0:
(d) CH0:
(e) CH0:
(f)
(g) CH0:
(h) CH0:
Figure 14.10 Bus Mode and Channel Priority in Priority Fixed Mode
CH1:
CH1:
CH1:
CH1:
CH1:
CH0:
CH1:
CH1:
CH1:
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Priority: CH0 > CH1
Cycle steal mode
Cycle steal mode
Cycle steal mode
Cycle steal mode
Cycle steal mode
Burst mode
Cycle steal mode
Burst mode
Burst mode
Cycle steal mode
Burst mode
Cycle steal mode
Burst mode
Burst mode
Burst mode
Burst mode
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CH0 transfer source
CH1 transfer source
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
DMA CH1
DMA CH0
DMA CH0
DMA CH0
DMA CH1
DMA CH1
DMA CH0
DMA CH1
Burst mode
Cycle steal
Cycle steal
DMA CH1
Cycle steal
Burst mode
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH1
DMA CH0
DMA CH0
DMA CH1
DMA CH0
DMA CH1
DMA CH1
DMA CH0
Cycle steal
DMA CH0
Burst mode
Burst mode
DMA CH0 DMA CH0
DMA CH0
DMA CH0
DMA CH1
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH0 and CH1
DMA CH0 and CH1
Burst mode
Cycle steal
DMA CH0
DMA CH0
Burst mode
DMA CH0
DMA CH0
DMA CH1
Burst mode
DMA CH
DMA CH0
DMA CH0
DMA CH0
Burst mode
DMA CH0
DMA CH0
DMA CH1
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH0
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH1
DMA CH1
DMA CH1
DMA CH1
Burst mode
Cycle steal
Burst mode
Cycle steal
Cycle steal
Cycle steal
Burst mode
Cycle steal
DMA CH1
DMA CH1
DMA CH1
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH1
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH1
DMA CH1
DMA CH1
DMA CH1
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU