R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 906
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 906 of 1694
- Download datasheet (9Mb)
19. Display Unit (DU)
19.3.19 CLAMP Signal Start Register (CLAMPSR)
The CLAMP signal start register (CLAMPSR) sets the rising edge position of the CLAMP signal.
For timing charts for the CLAMP signal and the DE signal, refer to section 19.5.6, CLAMP Signal
and DE Signal.
The value is retained during power-on reset and manual reset.
Internal update:
Internal update:
Rev.1.00 Jan. 10, 2008 Page 874 of 1658
REJ09B0261-0100
Bit
31 to 11 ⎯
10 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
CLAMPS Undefined R/W
31
15
—
—
R
R
0
0
30
—
14
—
R
R
0
0
Initial
Value
All 0
29
13
—
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
27
11
—
—
R
R
0
0
Internal
Update
⎯
Yes
R/W
26
10
—
—
O
R
0
R/W
25
—
—
R
O
0
9
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clamp Signal Start
The CLAMP signal rising edge position should
be set in dot clock units relative to the falling
edge of the HSYNC signal.
The CLAMP signal rises (setting + 1) cycles
after the falling edge of the HSYNC signal.
Hence the CLAMP signal cannot be made to
rise in the same cycle as the falling edge of the
HSYNC signal.
R/W
24
—
—
R
O
0
8
R/W
23
—
—
R
O
0
7
R/W
22
—
—
O
R
0
6
CLAMPS
R/W
21
—
—
O
R
0
5
R/W
20
—
—
R
O
0
4
R/W
19
—
—
R
O
0
3
R/W
18
—
—
R
O
0
2
R/W
17
—
—
O
R
0
1
R/W
16
—
—
O
R
0
0
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