R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 802
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16. Watchdog Timer and Reset (WDT)
(2)
• Requesting sources
• Branch address: H'A000 0000
• Operation until branching
Rev.1.00 Jan. 10, 2008 Page 770 of 1658
REJ09B0261-0100
⎯ A general exception other than a user break while the BL bit in SR is set to 1.
⎯ WDTCNT overflow when both the WT/IT and RSTS bits in WDTCSR are set to 1
The exception code H'020 is set in EXPEVT. After initializing VBR and SR, the processing
branches by setting PC = H'A000 0000.
During initialization, the VBR register is rest to H'0000 0000. The SR register is initialized
such that the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt
mask level bits (IMASK3 to IMASK0) are set to B'1111.
Then, the CPU and peripheral modules are initialized. For details, refer to the register
descriptions in the corresponding sections.
Manual Reset
Manual_reset()
{
}
EXPEVT = H'0000 0020;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;
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