R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 326

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 294 of 1658
REJ09B0261-0100
Bit
23
22
21
20
19
18
17
16
15
14
13
12
Name
IC007
IC006
IC005
IC004
IC003
IC002
IC001
—
IC115
IC114
IC113
IC112
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Clears masking of the
interrupt source of IRL3 to
IRL0 = HLLL (H'8).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HLLH (H'9).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HLHL (H'A).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HLHH (H'B).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HHLL (H'C).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HHLH (H'D).
Clears masking of the
interrupt source of IRL3 to
IRL0 = HHHL (H'E).
Reserved
This bit is always read as 0. The write value should
always be 0.
Clears masking of the
interrupt source of IRL7 to
IRL4 = LLLL (H'0).
Clears masking of the
interrupt source of IRL7 to
IRL4 = LLLH (H'1).
Clears masking of the
interrupt source of IRL7 to
IRL4 = LLHL (H'2).
Clears masking of the
interrupt source of IRL7 to
IRL4 = LLHH (H'3).
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
corresponding interrupt
mask (enables the
interrupt)