R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 30
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 30 of 1694
- Download datasheet (9Mb)
28.3 Usage Example ................................................................................................................ 1449
Section 29 User Break Controller (UBC)
29.1 Features............................................................................................................................ 1453
29.2 Register Descriptions....................................................................................................... 1455
29.3 Operation Description...................................................................................................... 1473
29.4 User Break Debugging Support Function ........................................................................ 1480
29.5 User Break Examples....................................................................................................... 1481
29.6 Usage Notes ..................................................................................................................... 1485
Section 30 User Debugging Interface (H-UDI)
30.1 Features............................................................................................................................ 1487
30.2 Input/Output Pins............................................................................................................. 1489
30.3 Register Description ........................................................................................................ 1491
Rev.1.00 Jan. 10, 2008 Page xxviii of xxx
REJ09B0261-0100
28.2.37 Port L Pull-Up Control Register (PLPUPR)..................................................... 1438
28.2.38 Port M Pull-Up Control Register (PMPUPR)................................................... 1439
28.2.39 Port N Pull-Up Control Register (PNPUPR) .................................................... 1440
28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ............................................. 1441
28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2) ............................................. 1441
28.2.42 Peripheral Module Select Register 1 (P1MSELR) ........................................... 1443
28.2.43 Peripheral Module Select Register 2 (P2MSELR) ........................................... 1447
28.3.1
28.3.2
28.3.3
29.2.1
29.2.2
29.2.3
29.2.4
29.2.5
29.2.6
29.2.7
29.2.8
29.2.9
29.3.1
29.3.2
29.3.3
29.3.4
29.3.5
29.3.6
30.3.1
Port Output Function ........................................................................................ 1449
Port Input function............................................................................................ 1450
Peripheral Module Function ............................................................................. 1451
Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ....................... 1457
Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ....................... 1463
Match Address Setting Registers 0 and 1 (CAR0 and CAR1).......................... 1465
Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)......... 1466
Match Data Setting Register 1 (CDR1) ............................................................ 1468
Match Data Mask Setting Register 1 (CDMR1)............................................... 1469
Execution Count Break Register 1 (CETR1).................................................... 1470
Channel Match Flag Register (CCMFR) .......................................................... 1471
Break Control Register (CBCR) ....................................................................... 1472
Definition of Words Related to Accesses ......................................................... 1473
User Break Operation Sequence ....................................................................... 1474
Instruction Fetch Cycle Break .......................................................................... 1475
Operand Access Cycle Break ........................................................................... 1476
Sequential Break............................................................................................... 1477
Program Counter Value to be Saved................................................................. 1479
Instruction Register (SDIR) .............................................................................. 1492
.................................................................... 1453
......................................................... 1487
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