R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 889

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.6
The color palette control register (CPCR) is a register which enables switching of the color palette.
For information on color palette switching, refer to section 19.4.8, Color Palettes.
Internal update:
Internal update:
Bit
31 to 20 ⎯
19
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Color Palette Control Register (CPCR)
Bit Name
CP4CE
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
Initial
Value
All 0
0
29
—
13
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
R/W
27
11
—
—
R
R
0
0
Internal
Update
⎯
Yes
26
10
—
—
R
R
0
0
25
—
—
R
R
0
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Color Palette 4 Change Enable
0: Switching of color palette 4 is not performed.
1: Switching of color palette 4 is performed.
24
—
—
R
R
0
8
0
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 4,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
23
—
—
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 857 of 1658
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
CP4CE
R/W
19. Display Unit (DU)
19
—
O
R
0
3
0
REJ09B0261-0100
CP3CE
R/W
18
—
O
R
0
2
0
CP2CE
R/W
17
—
O
R
0
1
0
CP1CE
R/W
16
—
O
R
0
0
0