R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 938
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 938 of 1694
- Download datasheet (9Mb)
19. Display Unit (DU)
19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6)
The plane n display area start address 1 registers (PnDSA1R, n = 1 to 6) set the memory area in
frame buffer 1 for plane n. The value is retained during power-on reset and manual reset.
Internal update:
Internal update:
Rev.1.00 Jan. 10, 2008 Page 906 of 1658
REJ09B0261-0100
Bit
31 to 4
3 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
PnDSA1
R/W
R/W
31
15
—
—
O
O
R/W
R/W
30
—
14
—
O
O
Initial
Value
Undefined R/W
All 0
R/W
R/W
29
13
—
—
O
O
R/W
R/W
28
12
—
—
O
O
R/W
R
R/W
R/W
27
11
—
—
O
O
Internal
Update
Yes
⎯
R/W
R/W
26
10
—
—
O
O
PnDSA1
R/W
R/W
25
—
—
O
O
9
Description
Plane n Display Area Start Address 1
To enable the 31 to 29 bits, the DSAE bit in
DEFR should be set to 1.
In the initial state the bits are not enabled, and
are fixed at 0.
When the buffer mode for plane n is manual
display change mode or auto display change
mode, the buffer is used as frame buffer 1.
Note: In 32-bit address extended mode, when
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
24
—
—
O
O
8
PnDSA1
the 31 to 29 bits in this register are
disabled, of the lower 29 bits of a specified
32-bit physical address, a 25-bit address
(A28 to A4) is specified in the 28 to 4 bits.
R/W
R/W
23
—
—
O
O
7
R/W
R/W
22
—
—
O
O
6
R/W
R/W
21
—
—
O
O
5
R/W
R/W
20
—
—
O
O
4
R/W
19
—
—
O
R
3
0
R/W
18
—
—
O
R
2
0
R/W
17
—
—
O
R
1
0
R/W
16
—
—
O
R
0
0
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