R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1240

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
24.3.18 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal.
The DMA request signal is output based on a value that has been set to SET2 to SET0.
Rev.1.00 Jan. 10, 2008 Page 1208 of 1658
REJ09B0261-0100
Bit
7
6
5 to 3
2
1
0
Bit Name
DMAEN
AUTO
⎯
SET2
SET1
SET0
Initial value:
Initial
Value
0
0
All 0
0
0
0
R/W:
Bit:
DMAEN
R/W
7
0
R/W
R/W
R/W
R
R/W
R/W
R/W
AUTO
R/W
6
0
Description
DMA Enable
0: Disables output of DMA request signal.
1: Enables output of DMA request signal.
Auto Mode for pre-define multiple block transfer using
DMA transfer
0: Disable auto mode
1: Enable auto mode
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Request Signal Assert Condition
Sets DMA request signal assert condition.
000: Not output
001: FIFO remained data is 1/4 or less of FIFO capacity.
010: FIFO remained data is 1/2 or less of FIFO capacity.
011: FIFO remained data is 3/4 or less of FIFO capacity.
100: FIFO remained data is 1 byte or more.
101: FIFO remained data is 1/4 or more of FIFO capacity.
110: FIFO remained data is 1/2 or more of FIFO capacity.
111: FIFO remained data is 3/4 or more of FIFO capacity.
⎯
R
5
0
⎯
4
0
R
⎯
R
0
3
SET2
R/W
2
0
SET1
R/W
1
0
R/W
SET0
0
0