R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1387

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
31 to 22
21, 20
19
Bit Name
—
FIFOTRG
[1:0]
AC1CLR
Initial
Value
All 0
00
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
FIFO Trigger Setting
Change the condition for the FIFO transfer request.
(1) In reading flash memory
(2) In writing flash memory
FLECFIFO Clear
Clears the address counter of FLECFIFO.
0: Retains the address counter value of FLECFIFO. In
1: Clears the address counter of FLECFIFO. After
flash-memory access, clear this bit to 0.
clearing the counter, clear this bit to 0.
00: Issue an interrupt to the CPU or a DMA transfer
01: Issue an interrupt to the CPU or a DMA transfer
10: Issue an interrupt to the CPU or a DMA transfer
11: Issue an interrupt to the CPU when FLDTFIFO
00: Issue an interrupt to the CPU when FLDTFIFO
01: Issue an interrupt or a DMA transfer request to
10: Issue an interrupt to the CPU when FLDTFIFO
11: Issue an interrupt to the CPU when FLDTFIFO
request when 4-byte data is written to
FLDTFIFO
request when 16-byte data is written to
FLDTFIFO
request when 128-byte data is written to
FLDTFIFO
stores 128 bytes of data, or issue a DMA
transfer request when FLDTFIFO stores 16
bytes of data
has 4 bytes or more of empty area (do not set
DMA transfer)
the CPU when FLDTFIFO has 16 bytes or more
of empty area
has 128 bytes or more of empty area (do not
set DMA transfer)
has 128 bytes or more of empty area, or issue a
DMA transfer request to the CPU when
FLDTFIFO has empty area of 16 bytes or more
27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1355 of 1658
REJ09B0261-0100