R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1525
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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30.3.3
SDBPR is a 1-bit register that supports the JTAG bypass mode. When the BYPASS command is
set to the boundary-scan TAP controller, SDBPR is connected between the TDI and TDO pins.
This register cannot be accessed through the CPU. This register is not initialized by a power-on
reset or assertion of TRST, but it is initialized to 0 by the Capture-DR state.
30.3.4
SDBSR is a register that supports the JTAG boundary scan mode. SDBSR is a shift register that is
located on the PAD, to control the input/output pins. By using the SAMPLE/PRELOAD and
EXTEST commands, this register can perform the boundary scan test that supports the JTAG
standard (IEEE 1149.1) with the subset. This register cannot be accessed through the CPU,
regardless of chip mode. This register is not initialized by a power-on reset or assertion of TRST.
Bit
15 to 1
0
Bypass Register (SDBPR)
Boundary Scan Register (SDBSR)
Bit Name
⎯
INTREQ
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Request
Indicates whether or not an interrupt by an H-UDI
interrupt command has occurred. Clearing this bit to 0
by the CPU cancels an interrupt request. When writing
1 to this bit, the previous value is maintained.
Rev.1.00 Jan. 10, 2008 Page 1493 of 1658
30. User Debugging Interface (H-UDI)
REJ09B0261-0100
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