R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 252

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8. Caches
8.2.4
RAMCR controls the number of ways in the IC and OC and prediction of the IC way.
RAMCR modifications must only be made by a program in the non-cacheable P2 area. After
RAMCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the cacheable area, the IL memory area, the OL memory area, or
the U memory area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating RAMCR, the specific instruction
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
Rev.1.00 Jan. 10, 2008 Page 220 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 10 ⎯
9
non-cacheable area, the IL memory area, the OL memory area, or the U memory area.
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after RAMCR
has been updated.
R/W:
R/W:
Bit:
Bit:
On-Chip Memory Control Register (RAMCR)
Bit Name
RMD
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
26
10
R
R
0
0
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
On-Chip Memory Access Mode Bit
For details, see section 9.4, On-Chip Memory
Protective Functions.
RMD
R/W
25
R
0
9
0
R/W
RP
24
R
0
8
0
IC2W OC2W
R/W
23
R
0
7
0
R/W
22
R
6
0
0
ICWPW
R/W
21
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0