R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 178

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
7.1.1
(1)
This LSI supports a 32-bit virtual address space, and can access a 4-Gbyte address space. The
virtual address space is divided into a number of areas, as shown in figures 7.2 and 7.3. In
privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode,
a 2-Gbyte space in the U0 area can be accessed. When the SQMD bit in the MMU control register
(MMUCR) is 0, a 64-Mbyte space in the store queue area can be accessed. When the RMD bit in
the on-chip memory control register (RAMCR) is 1, a 16-Mbyte space in on-chip memory area
can be accessed. Accessing areas other than the U0 area, store queue area, and on-chip memory
area in user mode will cause an address error.
When the AT bit in MMUCR is set to 1 and the MMU is enabled, the P0, P3, and U0 areas can be
mapped onto any physical address space in 1-, 4-, 64-Kbyte, or 1-Mbyte page units in TLB
compatible mode and in 1-, 4-, 8-, 64-, 256-Kbyte, 1-, 4-, or 64-Mbyte page units in TLB extended
mode. By using an 8-bit address space identifier, the P0, P3, and U0 areas can be increased to a
maximum of 256. Mapping from the virtual address space to the 29-bit physical address space is
carried out using the TLB.
Rev.1.00 Jan. 10, 2008 Page 146 of 1658
REJ09B0261-0100
Virtual Address Space
Address Spaces
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
Figure 7.2 Virtual Address Space (AT in MMUCR = 0)
Privileged mode
Non-cacheable
Non-cacheable
Cacheable
Cacheable
Cacheable
P0 area
P1 area
P2 area
P3 area
P4 area
address space
Physical
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
On-chip memory area
Store queue area
Address error
Address error
Address error
User mode
Cacheable
U0 area
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'FFFF FFFF