R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 408
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 408 of 1694
- Download datasheet (9Mb)
11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 376 of 1658
REJ09B0261-0100
Bit
6 to 4
3
2 to 0
Bit Name
BW
MPX
TYPE
Initial
Value
111
0
000
R/W
R/W
R/W*
R/W
Description
Burst Pitch
When the burst ROM interface is used, these bits
specify the number of wait cycles to be inserted after
the second data access in a burst transfer.
000: No idle cycle inserted, RDY pin disabled
001: 1 idle cycle inserted, RDY pin enabled
010: 2 idle cycles inserted, RDY pin enabled
011: 3 idle cycles inserted, RDY pin enabled
100: 4 idle cycles inserted, RDY pin enabled
101: 5 idle cycles inserted, RDY pin enabled
110: 6 idle cycles inserted, RDY pin enabled
111: 7 idle cycles inserted, RDY pin enabled
MPX Interface Setting
Selects the type of the MPX interface
0: Memory type set by bits TYPE2 to TYPE0 is selected
1: MPX interface is selected
Note: * The MPX bit in CS0BCR is read-only.
Memory Type Setting
These bits specify the type of memory connected to the
space.
000: SRAM (Initial value)
001: SRAM with byte-control*
010: Burst ROM (burst at read/SRAM at write)
011: Reserved (Setting prohibited)
100: PCMCIA *
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
Notes: 1. Setting enabled only in CS1BCR and
2. Setting enabled only in CS5BCR and
CS4BCR
CS6BCR
2
1
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