R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 707
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 707 of 1694
- Download datasheet (9Mb)
14.3.1
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the source address of the next transfer. A word or
longword boundary address should be specified when a word or longword transfer is performed
respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte or 32-byte
transfer is performed respectively.
In 29-bit address mode, the source address is changed as follows before it is output.
• The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used.
• The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used.
• The written address is output as it is when bits 31 to 29 are 111.
In 32-bit address mode, the written address is output as it is.
The initial value of SAR is undefined.
Initial value:
Initial value:
R/W:
R/W:
BIt:
BIt:
DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
R/W
R/W
31
15
⎯
⎯
R/W
R/W
30
14
⎯
⎯
R/W
R/W
29
13
⎯
⎯
R/W
R/W
28
⎯
12
⎯
R/W
R/W
27
⎯
11
⎯
R/W
R/W
26
10
⎯
⎯
R/W
R/W
25
⎯
⎯
9
R/W
R/W
24
⎯
⎯
8
R/W
R/W
23
⎯
⎯
7
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 675 of 1658
R/W
R/W
22
⎯
⎯
6
R/W
R/W
21
⎯
⎯
5
R/W
R/W
20
⎯
⎯
4
R/W
R/W
19
⎯
⎯
3
REJ09B0261-0100
R/W
R/W
18
⎯
⎯
2
R/W
R/W
17
⎯
⎯
1
R/W
R/W
16
⎯
⎯
0
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