R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1066

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21. Serial Communication Interface with FIFO (SCIF)
• Full-duplex communication capability
• LSB first for data transmission and reception
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of clock source: internal clock from baud rate generator or external clock from
• Four interrupt sources
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
• In asynchronous mode, modem control functions (SCIF0_RTS and SCIF0_CTS) are
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Rev.1.00 Jan. 10, 2008 Page 1034 of 1658
REJ09B0261-0100
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous
transmission and reception of serial data.
SCIF0_SCK to SCIF5_SCK pins
There are four interrupt sources – transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive error – that can issue requests independently.
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
provided.(only in channel 0)
the receive data in the receive FIFO register, can be ascertained.

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