R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 342

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
(4)
INT2MSKR is a 32-bit readable/writable register that can mask interrupts for sources indicated in
the interrupt source register. When a bit in this register is set to 1, the interrupt in the
corresponding bit is not notified. INT2MSKR is initialized to H'FFFF FFFF (all masked) by a
reset.
After this register is written to or the masking is cleared by writing to INT2MSKCLR, the timing
required to reflect the register value is guaranteed by reading from this register once.
Table 10.9 shows the correspondence between bits in INT2MSKR and the interrupts that are
masked.
Table 10.9 Correspondence between Bits in INT2MSKR and Interrupts that Are Masked
Rev.1.00 Jan. 10, 2008 Page 310 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to
29
28
27
26
25
24
23
22
21
20
19
R/W:
R/W:
Interrupt Mask Register (INT2MSKR)
Initial
Value R/W Source
All 1
1
1
1
1
1
1
1
1
1
1
Bit:
Bit:
R/W
31
15
⎯
R
1
1
R
R/W GDTA
R/W DU
R/W SSI channel 1 Masks the SSI channel 1 interrupt
R/W SSI channel 0 Masks the SSI channel 0 interrupt
R/W GPIO
R/W FLCTL
R/W MMCIF
R/W HSPI
R/W SIOF
R/W PCIC (5)
R/W
30
⎯
14
R
1
1
Reserved
R/W
29
⎯
13
R
1
1
R/W
R/W
28
12
1
1
R/W
R/W
27
11
1
1
Function
These bits are always read as 1.
The write value should always be 1.
Masks GDTA interrupt
Masks DU interrupt
Masks the GPIO interrupt
Masks the FLCTL interrupt
Masks the MMCIF interrupt
Masks the HSPI interrupt
Masks the SIOF interrupt
Masks PCIERR and PCIPWD3 to
PCIPWD0 interrupt
R/W
R/W
26
10
1
1
R/W
R/W
25
1
9
1
R/W
R/W
24
1
8
1
R/W
R/W
23
1
7
1
R/W
R/W
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
Description
Masks interrupt of each
on-chip peripheral
module
[When written]
0: Invalid
1: Interrupt is masked
[When read]
0: Not masked
1: Masked
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1