R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 777

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15.4.3
FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock
(lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus
clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck).
FRQMR1 can only be accessed in longwords.
This register is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
Note: The initial value (x: a bit whose value is undefined) depends on the settings of mode pins
Initial value:
Initial value:
Bit
31
30
29
28
27
26
25
24
23
22
21
20
R/W:
R/W:
BIt:
BIt:
MODE0 to MODE4, MODE11, and MODE12 on a power-on reset via the PRESET pin.
See Table 15.3 or 15.4.
Frequency Display Register 1 (FRQMR1)
Bit Name
IFST3
IFST2
IFST1
IFST0
UFST3
UFST2
UFST1
UFST0
SFST3
SFST2
SFST1
SFST0
MFST3 MFST2
IFST3 IFST2
31
15
R
R
0
0
30
14
R
R
0
0
MFST1
IFST1
29
13
R
R
0
1
Initial
Value
0
0
0
1
0
0
1
x
0
0
1
x
MFST0
IFST0
28
12
R
R
1
x
UFST3
S2FST3
R/W
R
R
R
R
R
R
R
R
R
R
R
R
27
11
R
R
0
0
UFST2
S2FST2
26
10
R
R
0
1
Description
Frequency division ratio of the CPU clock (Ick)
0001: × 1/2
0010: × 1/4
0011: × 1/6
Frequency division ratio of the RAM clock (Uck)
0010: × 1/4
0011: × 1/6
Frequency division ratio of the SuperHyway clock
(SHck)
0010: × 1/4
0011: × 1/6
UFST1
S2FST1
25
R
R
1
9
0
UFST0
S2FST0
24
R
R
8
x
x
SFST3
S3FST3
23
R
R
0
7
x
SFST2
S3FST2
Rev.1.00 Jan. 10, 2008 Page 745 of 1658
22
R
R
0
6
1
SFST1
S3FST1
21
R
R
1
5
x
15. Clock Pulse Generator (CPG)
SFST0
S3FST0
20
R
R
x
4
x
BFST3
PFST3
19
R
R
x
3
1
REJ09B0261-0100
BFST2
PFST2
18
R
R
x
2
0
BFST1
PFST1
17
R
R
x
1
x
BFST0
PFST0
16
R
R
1
0
x