R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 599

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
12
11
10, 9
8
7
Bit Name
RTA
STA
DEVSEL
MDPE
FBBC
Initial
Value
0
0
01
0
1
R/W
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
PCI: R
SH: R/WC
PCI: R/WC
SH: R
PCI: R
SH: R
Description
Target Abort Receive Status
This bit indicates that a transaction was completed by
target abort when the PCIC is a master.
0: Transaction is not completed with target abort
1: The bus master detected completion of transaction
Target Abort Execution Status
This bit indicates that a transaction was completed by
target abort when the PCIC is a target.
0: Transaction is not completed by target abort
1: Transaction was completed by target abort
DEVSEL Timing Status
This bit indicate the response timing status of
DEVSEL when the PCIC is a target.
00: Fast (not support)
01: Medium
10: Slow (not support)
11: Reserved
Data Parity Error
This bit indicates that the PCIC asserted PERR or
detected the assertion of PERR when the PCIC is a
master. This bit is set to 1 only when the parity
response bit is set to 1.
0: Data parity error is not generated
1: Data parity error was generated
Fast Back-to-Back Status
This bit indicates whether a target can accept fast
back-to-back transfers for a different target if the PCIC
is a target.
0: A target does not support fast back-to-back
1: A target supports fast back-to-back transactions for
with target abort.
transactions for a different target
a different target
Rev.1.00 Jan. 10, 2008 Page 567 of 1658
13. PCI Controller (PCIC)
REJ09B0261-0100