R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 175
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 175 of 1694
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7. Memory Management Unit (MMU)
Section 7 Memory Management Unit (MMU)
This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit or
32-bit physical address space. Address translation from virtual addresses to physical addresses is
enabled by the memory management unit (MMU) in this LSI. The MMU performs high-speed
address translation by caching user-created address translation table information in an address
translation buffer (translation lookaside buffer: TLB).
This LSI has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB
copies are stored in the ITLB by hardware. A paging system is used for address translation. It is
possible to set the virtual address space access right and implement memory protection
independently for privileged mode and user mode.
The MMU of this LSI runs in several operating modes. In view of physical address mapping
ranges, 29-bit address mode and 32-bit address extended mode are provided. In view of flag
functions of the MMU, TLB compatible mode (four paging sizes with four protection bits) and
TLB extended mode (eight paging sizes with six protection bits) are provided.
Selection between 29-bit address mode and 32-bit address extended mode is made by setting the
relevant control register (bit SE in the PASCR register) by software. This LSI supports 32-bit boot
mode (the system starts up in 32-bit address extended mode at power-on reset), which is specified
through external pins.
Selection between TLB compatible mode and TLB extended mode is made by setting the relevant
control register (bit ME in the MMUCR register) by software. The range of physical address
mapping is explained through sections 7.1, Overview of MMU, to 7.7, Memory-Mapped TLB
Configuration, for the case of 29-bit address mode, which is followed by section 7.8, 32-Bit
Address Extended Mode, where differences from 29-bit address mode are explained.
The flag functions of the MMU are explained in parallel for both TLB compatible mode and TLB
extended mode.
Rev.1.00 Jan. 10, 2008 Page 143 of 1658
REJ09B0261-0100
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