R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 11

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
1.1
1.2
1.3
1.4
1.5
Section 2 Programming Model
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Section 3 Instruction Set
3.1
3.2
3.3
Section 4 Pipelining
4.1
4.2
4.3
Section 5 Exception Handling
5.1
5.2
Features of the SH7785.......................................................................................................... 1
Block Diagram ..................................................................................................................... 13
Pin Arrangement Table ........................................................................................................ 14
Pin Arrangement .................................................................................................................. 22
Physical Memory Address Map ........................................................................................... 24
Data Formats........................................................................................................................ 25
Register Descriptions ........................................................................................................... 26
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Memory-Mapped Registers.................................................................................................. 39
Data Formats in Registers .................................................................................................... 40
Data Formats in Memory ..................................................................................................... 40
Processing States.................................................................................................................. 41
Usage Notes ......................................................................................................................... 43
2.7.1
Execution Environment ....................................................................................................... 45
Addressing Modes ............................................................................................................... 47
Instruction Set ...................................................................................................................... 52
Pipelines............................................................................................................................... 65
Parallel-Executability........................................................................................................... 76
Issue Rates and Execution Cycles........................................................................................ 79
Summary of Exception Handling......................................................................................... 89
Register Descriptions ........................................................................................................... 89
5.2.1
Privileged Mode and Banks .................................................................................. 26
General Registers.................................................................................................. 30
Floating-Point Registers ....................................................................................... 31
Control Registers .................................................................................................. 33
System Registers................................................................................................... 35
Notes on Self-Modifying Code............................................................................. 43
TRAPA Exception Register (TRA) ...................................................................... 90
.................................................................................................................. 1
............................................................................................................... 65
....................................................................................................... 45
............................................................................................ 89
........................................................................................... 25
Contents
Rev.1.00 Jan. 10, 2008 Page ix of xxx
REJ09B0261-0100