R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1121

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In serial transmission, the SCIF operates as follows.
1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is
4. After serial transmission ends, the SCIF_SCK pin is fixed high when the CKE1 bit in SCSCR
Figure 21.18 shows an example of the SCIF transmission operation.
Synchronization
clock
SCIF_SCK
Serial data
SCIF_TXD
TDFE
TEND
starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit
data to SCFTDR. The number of data bytes that can be written is at least 64 (transmit trigger
setting count).
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls to or below the transmit trigger count set in
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-
data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCIF outputs eight synchronization clock pulses for each
data.
When the external clock is selected, data is output in synchronization with the input clock.
The serial transmit data is sent from the SCIF_TXD pin in LSB-first order.
present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the
next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the
last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit.
is 0.
TXI interrupt
request
Figure 21.18 Example of SCIF Transmission Operation
Bit 0
LSB
Data written to SCFTDR
and TDFE flag cleared to 0
by TXI interrupt handler
Bit 1
One frame
MSB
Bit 7
TXI interrupt
request
21. Serial Communication Interface with FIFO (SCIF)
Bit 0
Rev.1.00 Jan. 10, 2008 Page 1089 of 1658
Bit 1
Bit 6
REJ09B0261-0100
Bit 7