R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 818

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17. Power-Down Mode
17.3.2
MSTPCR0 is a 32-bit readable/writable register that can specify whether each peripheral module
operates or is stopped. MSTPCR can be accessed only in longword.
This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT
overflow, or H-UDI reset.
Rev.1.00 Jan. 10, 2008 Page 786 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31, 30
29 to 24 MSTP[29:24]
23, 22
R/W:
R/W:
BIt:
BIt:
Standby Control Register 0 (MSTPCR0)
Bit Name
⎯
⎯
R/W
R/W
31
15
⎯
⎯
0
0
R/W
R/W
30
⎯
14
⎯
0
0
R/W
R/W
MSTP[13:12]
29
13
0
0
Initial
Value
All 0
All 0
All 0
R/W
R/W
28
12
0
0
R/W
R/W
MSTP[29:24]
27
11
⎯
0
0
R/W
R/W
R/W
R/W
R/W
R/W
26
10
⎯
0
0
R/W
R/W
25
MSTP[9:8]
0
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit [29:24]
Specify that the clock supply to the module of the
corresponding bit is stopped
[29]: SCIF channel 5, [28]: SCIF channel 4,
[27]: SCIF channel 3, [26]: SCIF channel 2,
[25]: SCIF channel 1, [24]: SCIF channel 0
0: The corresponding module operates
1: The clock to the corresponding module is
Reserved
These bits are always read as 0. The write value
should always be 0.
stopped
R/W
R/W
24
0
8
0
R/W
R/W
23
⎯
⎯
0
7
0
R/W
R/W
22
⎯
⎯
0
6
0
R/W
R/W
MSTP[21:20]
21
⎯
0
5
0
R/W
R/W
20
⎯
0
4
0
R/W
R/W
19
⎯
MSTP[3:2]
0
3
0
R/W
R/W
18
⎯
0
2
0
MSTP[17:16]
R/W
R/W
17
⎯
0
1
0
R/W
R/W
16
⎯
0
0
0