R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 876
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 876 of 1694
- Download datasheet (9Mb)
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 844 of 1658
REJ09B0261-0100
Bit
7, 6
5, 4
3 to 0
Bit Name
TVM
SCM
⎯
Initial
Value
10
00
All 0
R/W
R/W
R/W
R
Internal
Update
None
None
None
Description
TV Synchronization Mode
00: Master mode
01: Synchronization method switching mode
10: TV synchronization mode
11: Setting prohibited
Scan Mode
00: Non-interlace mode
01: Setting prohibited
10: Interlace sync mode
11: Interlace sync and video mode
Reserved
These bits are always read as 0. The write value
should always be 0.
HSYNC, VSYNC, CSYNC are output
When switching from TV sync mode to
master mode, or from master mode to TV
sync mode, is necessary, the switching
should pass through this mode. In this
mode, operation of the display system is
forcibly halted, and DISP outputs a low level
signal. Clock signal supply to the DCLKIN
pin can also be halted (input disabled)
(within the LSI the level is fixed high).
When a clock signal is supplied to the
DCLKIN pin, the clock is output from the
DCLKOUT pin.
The HSYNC pin is the EXHSYNC input, the
VSYNC pin is the EXVSYNC input, and the
ODDF pin is the ODDF input.
However, when the ODPM bit in DSMR is 1,
the ODDF pin output is clamped.
The HSYNC pin is the EXHSYNC input, the
VSYNC pin is the EXVSYNC input, and the
ODDF pin is the ODDF input.
However, when the ODPM bit in DSMR is 1,
the ODDF pin output is clamped.
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