R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1168

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
(2)
The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse (FS). In this
method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame
time has been passed (not the normal FS output timing) to transmit or receive control data. This
method is valid for SIOF slave mode. The following summarizes the control data interface
procedure by the secondary FS.
• Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears to 0).
• To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1
• The CODEC outputs the secondary FS.
• The SIOF transmits or receives (stores in SIRCDR) control data (data specified by SITCDR)
Figure 22.8 shows an example of the control data interface timing by the secondary FS.
SIOF_SYNC
Rev.1.00 Jan. 10, 2008 Page 1136 of 1658
REJ09B0261-0100
SIOF_RXD
SIOF_SCK
SIOF_TXD
by writing SITCDR).
synchronously with the secondary FS.
Control by Secondary FS (Slave Mode 2)
Specifications:
Normal FS
L-channel
Slot No.0
data
Figure 22.8 Control Data Interface (Secondary FS)
TRMD[1:0] = 01,
TDLE = 1,
RDLE = 1,
CD0E = 1,
LSB = 1 (Secondary FS request)
1/2 frame
REDG = 0
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
1 frame
Secondary FS
Slot No.0
channel 0
Control
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 0,
RDRE = 0,
CD1E = 0,
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000,
1/2 frame
Normal FS