R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 203

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note: When a value other than those listed above is recorded, operation is not guaranteed.
• V: Validity bit
• PPN: Physical page number
• EPR: Protection key data
0001: 4-Kbyte page
0010: 8-Kbyte page
0100: 64-Kbyte page
0101: 256-Kbyte page
0111: 1-Mbyte page
1000: 4-Mbyte page
1100: 64-Mbyte page
Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
Not affected by a manual reset.
Upper 19 bits of the physical address.
With a 1-Kbyte page, PPN[28:10] are valid.
With a 4-Kbyte page, PPN[28:12] are valid.
With a 8-Kbyte page, PPN[28:13] are valid.
With a 64-Kbyte page, PPN[28:16] are valid.
With a 256-Kbyte page, PPN[28:18] are valid.
With a 1-Mbyte page, PPN[28:20] are valid.
With a 4-Mbyte page, PPN[28:22] are valid.
With a 64-Mbyte page, PPN[28:26] are valid.
The synonym problem must be taken into account when setting the PPN (see section 7.5.5,
Avoiding Synonym Problems).
6-bit data expressing the page access right as a code.
Reading, writing, and execution (instruction fetch) in privileged mode and reading, writing,
and execution (instruction fetch) in user mode can be set independently. Each bit is disabled by
0 and enabled by 1.
EPR[5]: Reading in privileged mode
EPR[4]: Writing in privileged mode
EPR[3]: Execution in privileged mode (instruction fetch)
EPR[2]: Reading in user mode
Rev.1.00 Jan. 10, 2008 Page 171 of 1658
7. Memory Management Unit (MMU)
REJ09B0261-0100

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