R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 774

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15. Clock Pulse Generator (CPG)
15.4.2
FRQCR1 is a 32-bit readable/writable register that can select the division ratio of divider 2 for the
CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock
(DDRck), the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM
clock (Uck). To check the division ratio of divider 2 for each clock, read FRQMR1. FRQCR1 can
only be accessed in longwords.
FRQCR1 only changes the division ratio of a clock to which a value other than H'0 has been
written. Therefore, set a value other than H'0 in the bit corresponding to the clock for which you
want to change the division ratio. Other bits should be set to H'0.
To change the division ratio of each clock to the value set in FRQCR1, you must set 1 in the
FRQE bit in FRQCR0 to execute the sequence that changes the frequency. After the sequence is
executed, this register is automatically cleared to H'0000 0000.
However, when changing the division ratio of the DDR clock (DDRck), switch SDRAM to the
self-refreshing state. For details on how to switch to or release the self-refreshing state, see section
12, DDR2-SDRAM Interface (DBSC2).
FRQCR1 is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
Rev.1.00 Jan. 10, 2008 Page 742 of 1658
REJ09B0261-0100
Initial value:
Initial value:
R/W:
R/W:
BIt:
BIt:
Frequency Control Register 1 (FRQCR1)
MFC3 MFC2
IFC3
R/W
R/W
31
15
0
0
R/W
R/W
IFC2
30
14
0
0
MFC1
R/W
R/W
IFC1
29
13
0
0
MFC0
R/W
R/W
IFC0
28
12
0
0
S2FC3
UFC3
R/W
R/W
27
11
0
0
S2FC2
UFC2
R/W
R/W
26
10
0
0
S2FC1
UFC1
R/W
R/W
25
0
9
0
S2FC0
UFC0
R/W
R/W
24
0
8
0
S3FC3
SFC3
R/W
R/W
23
0
7
0
S3FC2
SFC2
R/W
R/W
22
0
6
0
S3FC1
SFC1
R/W
R/W
21
0
5
0
S3FC0
SFC0
R/W
R/W
20
0
4
0
BFC3
PFC3
R/W
R/W
19
0
3
0
BFC2
PFC2
R/W
R/W
18
0
2
0
BFC1
PFC1
R/W
R/W
17
0
1
0
BFC0
PFC0
R/W
R/W
16
0
0
0

Related parts for R8A77850ANBGV