R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 620

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE)
This register supports the functions specific to the PCI bridge and is required for all PCI-to-PCI
bridges.
Rev.1.00 Jan. 10, 2008 Page 588 of 1658
REJ09B0261-0100
Bit
7
6
5 to 0
Bit Name
BPCCEN
B2B3N
⎯
Initial value:
Initial
Value
0
0
All 0
PCI R/W:
SH R/W:
Bit:
R/W
SH: R
PCI: R
SH: R
PCI: R
SH: R
PCI: R
BPC
CEN
R
R
7
0
B2B3N
R
R
6
0
Description
When the bus power/clock control mechanism is
disabled, the system software does not use the power
state field in PCI_PMCSR of the bridge to control the
power or clock of the secondary bus of the bridge.
The state of this bit determines the action to be taken
as a result of programming that sets the power
management function to the D3 hot state.
0: Indicates that the power supplied to the secondary
1: Indicates that the PCI clock of the secondary bus
This bit is valid only when bit 7 (PCI_BPCCEN) is set
to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
—
R
R
5
0
will be stopped (B3) when the bridge function is set
to the D3 hot state.
will be stopped (B2) when the bridge function is set
to the D3 hot state.
—
R
R
4
0
—
R
R
3
0
—
R
R
2
0
—
R
R
1
0
—
R
R
0
0