R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 68

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2. Programming Model
(4)
Rev.1.00 Jan. 10, 2008 Page 36 of 1658
REJ09B0261-0100
Bit
31 to 22 —
21
20
19
18
Initial value:
Initial value:
Floating-Point Status/Control Register (FPSCR)
R/W:
R/W:
BIt:
BIt:
Bit Name
FR
SZ
PR
DN
R/W
31
15
R
0
0
R/W
30
14
R
0
0
Cause
R/W
Initial
Value
All 0
0
0
0
1
29
13
R
0
0
R/W
28
12
R
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
27
11
R
0
0
R/W
26
10
R
0
0
Enable (EN)
1: Denormalized number is treated as zero
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5.
Precision Mode
0: Floating-point instructions are executed as
1: Floating-point instructions are executed as
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5
Denormalization Mode
0: Denormalized number is treated as such
R/W
pair (64 bits)
single-precision operations
double-precision operations (graphics support
instructions are undefined)
XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1
are assigned to FR0 to FR15
FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1
are assigned to XF0 to XF15
25
R
0
9
0
R/W
24
R
0
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
R/W
R/W
FR
21
0
5
0
R/W
R/W
Flag
SZ
20
0
4
0
R/W
R/W
PR
19
0
3
0
R/W
R/W
DN
18
1
2
0
R/W
R/W
17
0
1
0
Cause
RM
R/W
R/W
16
0
0
1