R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 630

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(6)
PCIIR records interrupt sources. When an interrupt occurs, the corresponding bit is set to 1. When
multiple interrupts occur, only the first source is registered. When an interrupt is disabled, 1 is
written to the corresponding bit by the interrupt source, and no interrupt occurs.
Rev.1.00 Jan. 10, 2008 Page 598 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 15 ⎯
14
13 to 10 ⎯
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Interrupt Register (PCIIR)
Bit:
Bit:
Bit Name
TTADI
31
15
—
—
R
R
R
R
0
0
R/WC
TTA
30
—
14
DI
R
R
R
0
0
29
—
13
—
Initial
Value
All 0
0
All 0
R
R
R
R
0
0
28
12
—
—
R
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/WC
PCI: R
SH: R
PCI: R
27
11
—
—
R
R
R
R
0
0
26
10
—
—
R
R
R
R
0
0
R/WC
TMT
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
A target-abort is detected as an illegal byte enable
when the lower two bits (bits 1 and 0) of the address
and the byte enable do not match during an I/O
transfer (target).
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Reserved
These bits are always read as 0. The write value
should always be 0.
25
—
OI
R
R
R
0
9
0
R/WC
MDEI
24
—
R
R
R
0
8
0
R/WC
APE
23
—
DI
R
R
R
0
7
0
R/WC
SDI
22
—
R
R
R
0
6
0
R/WC
DPEI
TW
21
—
R
R
R
0
5
0
R/WC
PEDI
TR
20
—
R
R
R
0
4
0
R/WC
TAD
19
IM
—
R
R
R
0
3
0
R/WC
MAD
18
IM
—
R
R
R
0
2
0
R/WC
MW
PDI
17
—
R
R
R
0
1
0
R/WC
MRD
PEI
16
—
R
R
R
0
0
0