R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 121
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 121 of 1694
- Download datasheet (9Mb)
5.1
Exception handling processing is handled by a special routine which is executed by a reset,
general exception handling, or interrupt. For example, if the executing instruction ends
abnormally, appropriate action must be taken in order to return to the original program sequence,
or report the abnormality before terminating the processing. The process of generating an
exception handling request in response to abnormal termination, and passing control to a user-
written exception handling routine, in order to support such functions, is given the generic name of
exception handling.
The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2
Table 5.1 lists the configuration of registers related exception handling.
Table 5.1
Note:
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Non-support detection exception
register
*
Summary of Exception Handling
Register Descriptions
P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.
Register Configuration
Section 5 Exception Handling
Abbr.
TRA
EXPEVT
EXPMASK R/W
INTEVT
R/W
R/W
R/W
R/W
P4 Address*
H'FF00 0020
H'FF00 0024
H'FF00 0028
H'FF2F 0004
Rev.1.00 Jan. 10, 2008 Page 89 of 1658
Area 7
Address*
H'1F00 0020
H'1F00 0024
H'1F00 0028
H'1F2F 0004
5. Exception Handling
REJ09B0261-0100
Access Size
32
32
32
32
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