R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 821

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.3.3
MSTPCR1 is a 32-bit readable/writable register that each module of H-UDI, UBC, DMAC, and
GDTA operates or is stopped. MSTPCR1 can be accessed only in longword.
This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT
overflow, or H-UDI reset.
Initial value:
Initial value:
Bit
31 to 20 ⎯
19
18
17
R/W:
R/W:
BIt:
BIt:
Bit Name
MSTP119
⎯
MSTP117
Standby Control Register 1 (MSTPCR1)
R/W
R/W
31
15
⎯
⎯
0
0
R/W
R/W
30
14
⎯
⎯
0
0
R/W
R/W
29
13
⎯
⎯
0
0
Initial
Value
All 0
0
0
0
R/W
R/W
28
⎯
12
⎯
0
0
R/W
R/W
27
⎯
11
⎯
R/W
R/W
R/W
R/W
R/W
0
0
R/W
R/W
26
10
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit 119
Specifies that the clock supply to the H-UDI module is
stopped
0: H-UDI operates
1: H-UDI stopped
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit 117
Specifies that the clock supply to the UBC module is
stopped
0: UBC operates
1: UBC stopped
R/W
R/W
25
⎯
⎯
0
9
0
R/W
R/W
24
⎯
⎯
0
8
0
R/W
R/W
23
⎯
⎯
0
7
0
Rev.1.00 Jan. 10, 2008 Page 789 of 1658
R/W
R/W
22
⎯
⎯
0
6
0
MSTP[105:104]
R/W
R/W
21
⎯
0
5
0
R/W
R/W
20
⎯
0
4
0
MSTP119
17. Power-Down Mode
R/W
R/W
19
⎯
0
3
0
REJ09B0261-0100
R/W
R/W
18
⎯
⎯
0
2
0
MSTP117
R/W
R/W
17
⎯
0
1
0
MSTP100
R/W
R/W
16
⎯
0
0
0