UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 151

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Symbol
Symbol
P12
P12
P0
P2
P3
P6
P0
P2
P3
P6
Notes 1. If this pin is set as an analog input and to input mode, do not access the output latch.
Notes 1. If this pin is set as an analog input and to input mode, do not access the output latch.
Pmn
Pmn
7
0
0
0
0
0
7
0
0
0
0
0
0
1
0
1
2. “0” is always read from the output latch of the pin in the X1 oscillation mode or external clock
2. “0” is always read from the output latch of the pin in the X1 oscillation mode or external clock
Output 0
Output 1
Output 0
Output 1
input mode.
input mode.
6
0
0
0
0
0
6
0
0
0
0
0
Output data control (in output mode)
Output data control (in output mode)
P25
P125
P125
5
0
0
0
0
5
0
0
0
Figure 4-35. Format of Port Register (78K0/KA2-L)
Figure 4-34. Format of Port Register (78K0/KY2-L)
Note 1
P24
4
0
0
0
0
0
4
0
0
0
0
Preliminary User’s Manual U19111EJ2V1UD
Note 1
CHAPTER 4 PORT FUNCTIONS
P23
P23
3
0
0
0
0
3
0
0
0
0
Note 1
Note 1
m = 0, 2, 3, 6, 12; n = 0 to 3, 5
m = 0, 2, 3, 6, 12; n = 0 to 5
P122
P122
P22
P22
P32
2
0
0
0
2
0
0
Note 1
Note 1
Note 2
Note 2
P121
P121
P21
P21
P01
P61
P01
P31
P61
1
0
1
Note 1
Note 1
Note 2
Input low level
Input high level
Note 2
Input low level
Input high level
P20
P20
P00
P30
P60
P00
P30
P60
0
0
0
0
Note 1
Note 1
Input data read (in input mode)
Input data read (in input mode)
Address
Address
FF0CH
FF0CH
FF00H
FF02H
FF03H
FF06H
FF00H
FF02H
FF03H
FF06H
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
After reset
After reset
00H
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
151
R
R

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