UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 604
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UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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(b) Release by reset signal generation
Standby release signal
Note
Caution The above-mentioned oscillation accuracy stabilization wait time will be stated after the
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Caution The above-mentioned reset processing time will be stated after the device has been
Remark f
Internal high-speed
(X1 oscillation)
Status of CPU
oscillation clock
system clock
Reset signal
Status of CPU
High-speed
The wait time is as follows:
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is not carried out:
device has been evaluated.
is acknowledged.
evaluated.
X
Figure 19-6. STOP Mode Release by Interrupt Request Generation (2/2)
: X1 clock oscillation frequency
(3) When internal high-speed oscillation clock is used as CPU clock
(1) When high-speed system clock is used as CPU clock
Normal operation
(internal high-speed
system clock)
Oscillates
Normal operation
(high-speed
oscillation clock)
Figure 19-7. STOP Mode Release by Reset (1/2)
Oscillates
instruction
CHAPTER 19 STANDBY FUNCTION
Preliminary User’s Manual U19111EJ2V1UD
STOP
instruction
STOP
Oscillation stopped
STOP mode
Oscillation stopped
STOP mode
Interrupt
request
Oscillation
Starting X1 oscillation is
stopped
period
Reset
specified by software.
Wait
accuracy stabilization
Oscillation
processing
(TBD)
Wait for oscillation
stopped
Reset
Note
17 or 18 clocks
11 or 12 clocks
(TBD)
(internal high-speed
Normal operation
oscillation clock)
Oscillation stabilization time
(internal high-speed
Normal operation
oscillation clock)
Oscillates
(2
Oscillates
11
/f
X
to 2
16
/f
X
)
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