UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 595

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remarks 1.
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event counter 00
8-bit timer/event
counter
8-bit timer
Real-time counter (RTC)
Watchdog timer
Clock output
A/D converter
Operational amplifiers 0, 1
Serial interface
Key interrupt
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
IL
2.
HALT Mode Setting
f
f
f
The functions mounted depend on the product. Refer to 1.4 Block Diagram and 1.5 Outline of
Functions.
IH
EXCLK
EXCLKS
:
UART6
CSI10
CSI11
IICA
: External main system clock,
: External subsystem clock,
f
f
f
f
f
Internal high-speed oscillation clock,
IH
X
EXCLK
XT
EXCLKS
50
51
H0
H1
Clock supply to the CPU is stopped
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Operates or stops by external clock input
Status before HALT mode was set is retained
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable
Table 19-1. Operating Statuses in HALT Mode (1/2)
When CPU Is Operating on
Oscillation Clock (f
Internal High-Speed
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
CHAPTER 19 STANDBY FUNCTION
Preliminary User’s Manual U19111EJ2V1UD
IH
)
Status before HALT mode was set is retained
Operation continues (cannot
be stopped)
When CPU Is Operating on
f
f
f
X
XT
IL
: X1 clock
: Internal low-speed oscillation clock
: XT1 clock
X1 Clock (f
X
)
Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)
External Main System Clock
When CPU Is Operating on
(f
EXCLK
)
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