UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 210

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.8 Time required for switchover of CPU clock and main system clock
can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system
clock can be changed.
pre-switchover clock for several clocks (refer to Table 5-8 and 5-9).
(CLS) of the PCC register.
210
CSS PCC2 PCC1 PCC0
Set Value Before
PCC2
0
1
Set Value Before
0
0
0
0
1
Note 78K0/KC2-L only
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the
Whether the CPU is operating on the main system clock or the subsystem clock
Remark The number of clocks listed in Table 5-8 is the number of CPU clocks before switchover.
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
Remark 1. The number of clocks listed in Table 5-9 is the number of CPU clocks before switchover.
Switchover
Switchover
Table 5-8. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
Table 5-9. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
0
0
0
0
1
PCC1
0
0
1
1
0
0
0
1
1
0
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
0
1
0
1
0
PCC0
0
1
0
1
0
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
PCC2
8 clocks
4 clocks
2 clocks
2 clocks
1 clock
0
0
8 clocks
4 clocks
2 clocks
1 clock
0
PCC1
0
0
PCC0
0
0
(78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L)
16 clocks
4 clocks
2 clocks
2 clocks
1 clock
0
PCC2
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
0
0
16 clocks
4 clocks
2 clocks
1 clock
PCC1
1
0
(78K0/KC2-L)
0
PCC0
1
16 clocks
8 clocks
2 clocks
2 clocks
Set Value After Switchover
1 clock
0
Set Value After Switchover
PCC2
1
0
16 clocks
8 clocks
2 clocks
0
1 clock
PCC1
1
0
16 clocks
8 clocks
4 clocks
2 clocks
1 clock
PCC0
0
0
1
PCC2
0
1
16 clocks
Note
8 clocks
4 clocks
1 clock
0
PCC1
can be ascertained using bit 5
1
16 clocks
8 clocks
4 clocks
2 clocks
2 clocks
1
PCC0
1
0
0
PCC2
1
f
1
f
f
f
XP
16 clocks
f
XP
XP
XP
8 clocks
4 clocks
2 clocks
XP
/16f
/2f
/4f
/8f
/f
PCC1
SUB
0
SUB
SUB
SUB
SUB
clocks
clocks
clocks
clocks
clocks
PCC0
0