UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 606

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

is generated.
circuit voltage detection, and each item of hardware is set to the status shown in Tables 20-1 and 20-2. Each pin is
high impedance during reset signal generation or during the oscillation stabilization time just after a reset release.
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (refer to Figures 20-2 to 20-4) after reset processing. Reset by POC and LVI
circuit power supply detection is automatically released when V
execution starts using the internal high-speed oscillation clock (refer to CHAPTER 21 POWER-ON-CLEAR CIRCUIT
and CHAPTER 22 LOW-VOLTAGE DETECTOR) after reset processing.
606
The reset function is mounted onto all 78K0/Kx2-L microcontroller products.
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage from external
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
Note 78K0/KC2-L only
input pin (EXLVI pin), and detection voltage
2. During reset signal generation, the X1 clock, XT1 clock
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held
(If an external reset is effected upon power application, the period during which the supply
voltage is outside the operating range (V
low-level input may be continued before POC is released.)
clock, and internal low-speed oscillation clock stop oscillating. External main system clock
input and external subsystem clock
during reset input.
impedance.
CHAPTER 20 RESET FUNCTION
Preliminary User’s Manual U19111EJ2V1UD
However, because SFR is initialized, the port pins become high-
Note
input become invalid.
DD
< 1.8 V) is not counted in the 10 s. However, the
DD
V
POR
or V
DD
Note
, internal high-speed oscillation
V
LVI
after the reset, and program