UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 461

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) IICA flag register 0 (IICAF0)
This register sets the operation mode of I
IICAF0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits
are read-only.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I
register 0 (IICACTL0) = 0). When operation is enabled, the IICAF0 register can be read.
Reset signal generation clears this register to 00H.
Remark
Condition for clearing (ACKD0 = 0)
Condition for clearing (STD0 = 0)
Condition for clearing (SPD0 = 0)
ACKD0
When a stop condition is detected
At the rising edge of the next byte’s first clock
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
When a stop condition is detected
At the rising edge of the next byte’s first clock
following address transfer
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a
start condition
When IICE0 changes from 1 to 0 (operation stop)
Reset
STD0
SPD0
0
1
0
1
0
1
LREL0: Bit 6 of IICA control register 0 (IICACTL0)
IICE0:
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (3/3)
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Bit 7 of IICA control register 0 (IICACTL0)
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
Condition for setting (STD0 = 1)
Condition for setting (SPD0 = 1)
After the SDAA0 line is set to low level at the rising
edge of SCLA0’s ninth clock
When a start condition is detected
When a stop condition is detected
2
C is disabled (bit 7 (IICE0) of IICA control
2
C bus.
461