UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 184

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8) Oscillation stabilization time select register (OSTS)
184
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Address: FFA4H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
Figure 5-11. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
1
1
After reset: 05H
Other than above
2. Do not change the value of the OSTS register during the X1 clock oscillation
3. The oscillation stabilization time counter counts up to the oscillation
4. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
before executing the STOP instruction.
stabilization time.
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
clock oscillation starts (“a” below).
OSTS1
6
0
0
1
1
0
0
X1 pin voltage
waveform
Desired OSTC oscillation stabilization time
set by OSTS
R/W
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
OSTS0
5
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
Setting prohibited
11
13
14
15
16
/f
/f
/f
/f
/f
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
OSTS2
2
204.8 s
819.2 s
1.64 ms
3.27 ms
6.55 ms
Oscillation stabilization time
OSTS1
f
X
1
= 10 MHz
OSTS0
0