UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 191

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Subsystem clock (f
(when XT1 oscillation
(when X1 oscillation
Internal high-speed
oscillation clock (f
Internal reset signal
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
Notes 1.
<2> When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
<4> Set the start of oscillation of the X1 or XT1 clock via software (refer to (1) in 5.6.1 Example of controlling
system clock (f
Power supply
voltage (V
selected)
High-speed
CPU clock
oscillator automatically starts oscillation.
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
high-speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
switching via software (refer to (3) in 5.6.1 Example of controlling high-speed system clock and (3) in
5.6.3 Example of controlling subsystem clock).
selected)
2.
3.
Note 3
DD
SUB
0 V
XH
IH
Figure 5-16. Clock Generator Operation When Power Supply Voltage Is Turned On
)
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
78K0/KC2-L only
)
)
)
<1>
(When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0))
1.61 V
(TYP.)
<3> Waiting for
voltage stabilization
<2>
0.5 V/ms
(MIN.)
Note 1
1.8 V
Starting X1 oscillation
is set by software.
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
Starting XT1 oscillation
is set by software.
Internal high-speed oscillation clock
<4>
Reset processing
oscillation stabilization time:
<4>
2
8
/f
X
X1 clock
to 2
18
/f
X
Note 2
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock
Note 3
191

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