UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 459

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) IICA status register 0 (IICAS0)
Address: FFAAH
Symbol
IICAS0
This register indicates the status of I
IICAS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Caution Reading the IICA status register 0 (IICAS0) while WUP of IICA control register 1 (IICACTL1) is
Remark
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits
Condition for clearing (MSTS0 = 0)
Condition for clearing (ALD0 = 0)
set to 1 is prohibited. When WUP is changed from 0 to 1, regardless of the INTIICA0 interrupt
request, the change in status is not reflected until the next start condition or stop condition
is detected. To use the wakeup mode, therefore, enable (SPIE0 = 1) the interrupt generated
by detecting a stop condition and read the IICAS0 register after the interrupt has been
detected.
MSTS0
MSTS0
Automatically cleared after IICAS0 is read
When IICE0 changes from 1 to 0 (operation stop)
Reset
When a stop condition is detected
When ALD0 = 1 (arbitration loss)
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
ALD0
<7>
0
1
0
1
other than IICAS0. Therefore, when using the ALD0 bit, read the data of this bit before the data
of the other bits.
LREL0:
IICE0:
After reset: 00H
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (1/3)
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
ALD0
<6>
Bit 6 of IICA control register 0 (IICACTL0)
Bit 7 of IICA control register 0 (IICACTL0)
CHAPTER 15 SERIAL INTERFACE IICA
EXC0
Preliminary User’s Manual U19111EJ2V1UD
<5>
2
C.
R
COI0
<4>
Note
Detection of arbitration loss
TRC0
<3>
Master status
Condition for setting (MSTS0 = 1)
Condition for setting (ALD0 = 1)
When a start condition is generated
When the arbitration result is a “loss”.
ACKD0
<2>
STD0
<1>
SPD0
<0>
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