UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 198

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

198
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
(a) To execute a STOP instruction
(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop
Executing the STOP instruction to set the STOP mode
Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
<1> Setting of peripheral hardware
<2> Setting the X1 clock oscillation stabilization time after standby release
<3> Executing the STOP instruction
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the internal high-speed oscillation clock (RCM register)
78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L
78K0/KC2-L
MCS
CLS
0
1
0
0
1
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, refer to CHAPTER 19 STANDBY FUNCTION).
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed. To operate the CPU immediately after the STOP mode has been released,
set MCM0 to 0, switch the CPU clock to the internal high-speed oscillation clock, and check that
RSTS is 1.
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to a clock other than the internal high-speed oscillation clock.
When RSTOP is set to 1, internal high-speed oscillation clock is stopped.
peripheral hardware that is operating on the internal high-speed oscillation clock.
Internal high-speed oscillation clock
High-speed system clock
MCS
×
0
1
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
CPU Clock Status
CPU Clock Status