UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 335
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UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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9.4 Operation of Watchdog Timer
9.4.1 Controlling operation of watchdog timer
1.
2.
3.
4.
5.
Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before
When the watchdog timer is used, its operation is specified by the option byte (0080H).
After a reset release, the watchdog timer starts counting.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the
option byte, the watchdog timer is cleared and starts counting again.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
is written during a window close period, an internal reset signal is generated.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1
(the counter starts operating after a reset release) (for details, refer to CHAPTER 24).
Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, refer to
9.4.2 and CHAPTER 24).
Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
details, refer to 9.4.3 and CHAPTER 24).
If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
If data other than “ACH” is written to WDTE
If the instruction is fetched from an area not set by the IMS register (detection of an invalid check during a
CPU program loop)
If the CPU accesses an area not set by the IMS register (excluding FB00H to FFFFH) by executing a
read/write instruction (detection of an abnormal access during a CPU program loop)
WDTON
0
1
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH).
the overflow time regardless of the timing of the writing, and the watchdog timer starts
counting again.
different from the overflow time set by the option byte by up to 2/f
Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Operation Control of Watchdog Timer Counter/Illegal Access Detection
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 9 WATCHDOG TIMER
IL
seconds.
335
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