UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 208

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution
(10) HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
208
(B)
(C)
(D)
Status Transition
(D)
(D)
(B)
(C)
Note 78K0/KC2-L only
Note 78K0/KC2-L only
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figure 5-18 and 5-19.
HALT mode (F) set while CPU is operating with high-speed system clock (C)
HALT mode (G) set while CPU is operating with subsystem clock (D)
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(E)
(F)
(G)
(H)
(C) (X1 clock)
(C) (external main system clock)
(I)
already been set.
(Setting sequence of SFR registers)
Note
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer
to CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET VALUES)).
Setting Flag of SFR Register
2. EXCLK, OSCSEL:
Status Transition
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (4/4)
(Setting sequence)
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
Unnecessary if these
registers are already
EXCLK
0
1
Bits 7 and 6 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
set
OSCSEL
1
1
the high-speed system
CPU is operating with
MSTOP
Unnecessary if the
0
0
clock
Must not be
Register
checked
Must be
checked
OSTC
Setting
Setting
Note
Executing STOP instruction
register is already set
XSEL
Unnecessary if this
Note
1
1
Note
MCM0
1
1
CSS
0
0