UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 627

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Port mode register 12 (PM12) (78K0/KB2-L and 78K0/KC2-L only)
22.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
The low-voltage detector can be used in the following two modes.
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
If LVISEL = 0, compares the supply voltage (V
signal when V
If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and LVI detection voltage (V
generates an internal reset signal when EXLVI < V
Remarks 1. The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to
Note
Address: FF2CH
Symbol
PM12
Figure 22-4. Format of Port Mode Register 12 (PM12) (78K0/KB2-L and 78K0/KC2-L only)
This is a preliminary value and subject to change.
2. Level detection of input voltage from external input pin (EXLVI) is available only in 78K0/KB2-L
PM120
raise the power supply from the POC detection voltage (V
internal reset signal is generated when the supply voltage (V
V 0.1 V
detection voltage (V
and 78K0/KC2-L.
DD
7
1
0
1
< V
After reset: FFH
LVI
, and releases internal reset when V
Output mode (output buffer on)
Input mode (output buffer off)
Note
). After that, the internal reset signal is generated when the supply voltage (V
6
1
CHAPTER 22 LOW-VOLTAGE DETECTOR
LVI
Preliminary User’s Manual U19111EJ2V1UD
= 1.91 V 0.1 V
R/W
5
1
DD
) and LVI detection voltage (V
P120 pin I/O mode selection
4
1
EXLVI
Note
).
, and releases internal reset when EXLVI
DD
3
1
V
LVI
.
2
1
POR
DD
) < detection voltage (V
= 1.61 V (TYP.)) or lower, the
LVI
), generates an internal reset
1
1
PM120
0
V
EXLVI
LVI
.
= 1.91
EXLVI
DD
627
) <
),