UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 207

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
Status Transition
(C)
Status Transition
(C)
(C)
Status Transition
(D)
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figure 5-18 and 5-19.
Note 78K0/KC2-L only
Note 78K0/KC2-L only
(B)
(D) (XT1 clock)
(D) (external subsystem clock)
(B)
2. MCM0:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
XTSTART, CSS:
:
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (3/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Setting Flag of SFR Register
Bits 7 and 0 of the internal oscillation mode register (RCM)
Bits 6 and 4 of the processor clock control register (PCC)
Bit 0 of the main clock mode register (MCM)
Don’t care
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
Unnecessary if the CPU is operating
XTSTART
with the internal high-speed oscillation clock
RSTOP
with the internal high-speed
0
1
0
Unnecessary if the CPU is operating
RSTOP
0
Unnecessary if the CPU is operating
oscillation clock
0
with the subsystem clock
EXCLKS
Confirm this flag
0
1
RSTS
is 1.
Confirm this flag is 1.
OSCSELS
RSTS
1
1
Unnecessary if
XSEL is 0
MCM0
Note
0
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
Note
MCM0
0
CSS
0
CSS
1
1
207