UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 192

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

192
Subsystem clock (f
(when XT1 oscillation
Internal high-speed
(when X1 oscillation
oscillation clock (f
Internal reset signal
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
Cautions 1.
Remark
<2> When the power supply voltage exceeds 1.91 V (TYP.), the reset is released and the internal high-speed
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-
<4> Set the start of oscillation of the X1 or XT1 clock via software (refer to (1) in 5.6.1 Example of controlling
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
system clock (f
Power supply
voltage (V
selected)
High-speed
CPU clock
oscillator automatically starts oscillation.
speed oscillation clock.
high-speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
switching via software (refer to (3) in 5.6.1 Example of controlling high-speed system clock and (3) in
5.6.3 Example of controlling subsystem clock).
selected)
Note 3
2.
DD
SUB
0 V
XH
While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings.
stopped by executing the STOP instruction (refer to (4) in 5.6.1 Example of controlling high-speed
system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
5.6.3 Example of controlling subsystem clock).
IH
Figure 5-17. Clock Generator Operation When Power Supply Voltage Is Turned On
)
)
)
)
It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK and EXCLKS pins is used.
(When LVI Default Start Function Enabled Is Set (Option Byte: LVISTART = 1))
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the
voltage reaches 1.8 V, or set the LVI default start function enabled by using the option byte
(LVISTART = 1) (refer to Figure 5-17). When a low level has been input to the RESET pin until
the voltage reaches 1.8 V, the CPU operates with the same timing as <2> and thereafter in
Figure 5-16, after the reset has been released by the RESET pin.
<1>
The internal high-speed oscillation clock and high-speed system clock can be
1.91 V (TYP.)
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
Starting X1 oscillation
is set by software.
Note 1
<3>
<2>
Starting XT1 oscillation
is set by software.
<4>
oscillation stabilization time:
Reset processing
<4>
Internal high-speed
oscillation clock
2
8
/f
X
X1 clock
to 2
18
/f
X
Note 2
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock
Note 3